module openmips_min_sopc(
	input wire clk,
	input wire rst
);
	//CPU 指存连接线
	wire[31:0] openmips_inst_rom_inst;
	wire[31:0] openmips_inst_rom_addr;
	wire openmips_inst_rom_ce;
	//*************************
	
	//实例化MIPSCPU
	openmips openmips0(
		.clk(clk),
		.rst(rst),
		.inst_i(openmips_inst_rom_inst),
		.rom_ce_o(openmips_inst_rom_ce),
		.rom_addr_o(openmips_inst_rom_addr)
	);
	
	//实例化指存
	inst_rom inst_rom0(
		.ce(openmips_inst_rom_ce),
		.addr(openmips_inst_rom_addr),
		.inst(openmips_inst_rom_inst)
	);

endmodule